The invention relates to a method and an apparatus for producing a reference voltage that is applied to reference voltage inputs on receiver units in order to discriminate between the logic states of a data signal that is transmitted to a receiver end. A transmission device transmits, in addition to the data signal, a clock signal to the receiver end. The receiver end has an integrator that integrates the clock signal and produces the reference voltage from the integrated value. Such a method and an apparatus of this kind are known from the earlier German application 102 16 615.3 from Infineon Technologies AG.
In every signal-transmitting system, be it a bi-directional system or a unidirectional system, a driver uses a line or transmission link to send a signal from a first point to a second point, where the signal is received. Similarly, in a bi-directional system, a signal can be sent from a second point to the first point in the transmission link or in the transmission line, where it is likewise received and then decoded. In the simplest case, a receiver unit decodes the signal by converting it into a respective known level according to its logic state. To this end, the output of the receiver unit is switched between the two known signal levels, depending on whether or not the received signal level exceeds a particular threshold value (for example in the form of a reference voltage).
In ordinary systems, the reference voltage Vref is typically produced outside of a chip, is supplied thereto in the form of a predetermined voltage value and is applied to the receiver units therein. Normally, the value of the reference voltage is placed in the center between the received data signal's ideal maximum value and minimum value independently of the leading and trailing edges of the received data signal. However, there are a series of influencing variables that cause the reference voltage Vref to differ from this mean value. Such differences may be brought about by changes in the produced and received reference voltage itself and by the waveform of the received data signals.
By far the most frequent source of influence is differences between the drivers which drive the data signals. In many systems, even the way in which the data signals are terminated causes differences. If the drivers of the data signals have an asymmetrical driver resistance for high and low levels and/or if the terminating resistance results in asymmetrical termination for high and low levels, then the received data signal is not centered about its mean value, that is to say about the value of the reference voltage Vref produced. This results in less than optimum timing tolerances, particularly in DDR memory systems, in which the data signals' leading and trailing edges are expected to be totally symmetrical.
The method described in the aforementioned earlier application DE 102 16 615.3, involves the reference voltage Vref being produced directly by integrating the data strobe signal arriving on the chip. In this case, the problem may arise that if the receiver that uses the reference voltage produced by integration is not operating in optimum fashion, it is not possible to establish that the data signal that is output by the receivers is consequently not optimum. Hence this known method operates correctly only if the receiver using the reference voltage produced is perfect. A perfect receiver would react to the received data precisely at their point of intersection with the reference voltage produced and hence in the same way to rising and falling edges in the data signals. Hence, a perfect receiver of this kind would not change its delay if the reference voltage were to fluctuate. Real receivers are not perfect in this way, however, and therefore do not produce a perfect data output signal having a duty ratio of 50% even when the reference voltage is precisely in the center between an incoming data signal's high and low signal states of respectively equal duration.